Devangkumar Jariwala

Contact Information

Education

Publications

• Open Source Software:
1. RBI: An open source software implementing simultaneous placement and routing algorithm for FPGAs based on my ICCAD-04 paper is available for free. Please contact me by email to obtain the source code.
• Journal Articles:
1. Devang Jariwala, John Lillis, " RBI: A Simultaneous Placement and Routing Optimization Technique ," submitted to IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
• Conference Articles:
1. Qinzhou (Ben) Wang, Devang Jariwala, John Lillis, "A Study of Tighter Lower Bounds in LP Relaxation Based Placements," to appear at GLSVLSI, 2005.
2. Devang Jariwala, John Lillis, "On Interactions Between Routing and Detailed Placement," International Conference on Computer Aided Design, 2004.

Experience

Projects

• Research Projects

• Routability Analysis and Optimization in Placement/Floorplanning and Routing

Early prediction and optimization of routability is very important in current designs. This work focuses on devising framework for routability analysis and bridging the gap between placement and routing phases by early routability optimization. I have put up a short abstract of my thesis.

• Enhancements to the Mongrel Placement Tool

Mongrel is a hybrid tool for placement in standard cell desings. The current focus of this work is to improve basic framework with enhanced clustering techniques, novel search techniques and whitespace handling capabilities.

• Clustering in force directed placement framework

Working at Intel Corporation, designed and implemented clustering strategy to reduce the runtime complexity of the placement algorithm.

• Course Projects

• Incremental Reconfiguration in Multi-Module FPGA Systems

  An ILP based framework, employing Simplex Solver, was proposed to support efficient addition and deletion of nets from a system already implemented in multi-module FPGA environment.

• Asymmetric Travelling Salesman Problem

  An approach based on P-Tree and Interleaving algorithm was proposed for solving the celebrated problem of Asymmetric Travelling Salesman.

• Modeling CISC Processor in VHDL

  Employing Synopsys tool, 16-bit processor was modeled supporting indirect addressing mode.

Professional Activities

• Reviewer:
• IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)
• ACM Transactions on Design Automation of Electronic Systems (TODAES)
• Student Member:
• IEEE, Circuit and Systems Society
• ACM

Awards/Honors

• Second place winner at ACM CADathlon, CAD programming contest at ICCAD 2002
• Membership nomination to National Honor Society Phi Kappa Phi
• DAC Young Student Support Program Award winner at DAC 2001
• Awarded several Gold Medals for securing First rank in undergraduate studies
• Best Paper Award receipient at Mindbend 1997, Technical Symposium organized by REC-Surat.

Skills

Relevant Courses

• VLSI Design Automation
• Special topics in combinatorial optimization
• Special topics in circuit synthesis
• Computer Algorithms
• Object oriented languages and environment
• Computer systems design
• Principles of VLSI design
• Parallel processing
• High performance processors and systems

References

• Prof. John Lillis, Associate Professor, Computer Science Department, UIC.
• Prof. Florin Balasa, Assistant Professor, Computer Science Department, UIC.
• Dr. William Halpin, Sr. Staff Engineer, Synplicity Inc.