This section gives a description of the
file format used to specify layer/via parasitics and
the buffer library for topology synthesis and optimization.
Technology File (.tech file)
The .tech file is used to specify (i)
supply voltage(s),
(ii) routing layer direction, dimensions, dielectric context
and parasitics, and (iii) via parasitics,
which are to be used by the optimization engines. The file format is shown below :-
TECH_NAME <tech_name>
NUM_LAYERS <numlayers>
NUM_VIATYPES <numviatypes>
NUM_SUPPLIES <numsupplies>
# Information on routing layers
BEGIN_LAYER
NAME <layer_name>
ID <lid>
SHEET_RESISTANCE <R> (ohms/square)
UNIT_AREA_CAPACITANCE <Ca> (F/m^2)
[UNIT_INDUCTANCE <L> (H/m)]
UNIT_COUPLING_CAPACITANCE
<Cc> (F/m, assuming minimum-spacing, minimum-width wires)
UNIT_FRINGE_CAPACITANCE <Cf> (F/m)
[PERM_ILD_INTRALAYER<perm_ild_intralayer>]
[ILD_HEIGHT_ABOVE <ild_height_above > (meters)]
[PERM_ILD_ABOVE<perm_ild_above>]
[ILD_HEIGHT_BELOW <ild_height_below > (meters)]
[PERM_ILD_BELOW<perm_ild_below>]
[PREFERRED_DIR <H/V >]
LAYER_THICKNESS <thickness> (meters)
WIRE_SIZING <DISCRETE/CONTINUOUS>
WIDTHS <w_1> <w_2> ....
<w_n>
MIN_WIDTH <min_width>
MAX_WIDTH <max_width>
MIN_SPACING <min_spacing>
[CAP_TABLEDIMENSIONS N1 N2
CAP_TABLEAXIS1 width1, width2, ..., widthM
CAP_TABLEAXIS2 spacing1, spacing2, ..., spacingN
CAP_TABLEENTRIES
(( area11 fringe11 coupling11 ) ... (area1N fringe1N coupling1N))
(( area21 fringe21 coupling21 ) ... (area2N fringe2N coupling2N))
...
(( areaM1 fringeM1 couplingM1 ) ... (areaMN fringeMN couplingMN)) ]
END_LAYER
# Information on Via Types
BEGIN_VIATYPE
VIATYPE_NAME <viatype_name>
LOWER_LAYER <layer_id>
[LOWER_FOOTPRINT <dx, dy]>
UPPER_LAYER <layer_id>
[UPPER_FOOTPRINT <dx, dy]>
VIATYPE_RESISTANCE <r (ohms)>
VIATYPE_CAPACITANCE <c (farads)>
VIATYPE_INDUCTANCE <c (henrys)>
END_VIATYPE
# Information on Supplies
BEGIN_SUPPLIES
SUPPLY <supplyId, voltage>
SUPPLY <supplyId, voltage>
SUPPLY <supplyId, voltage>
END_SUPPLIES
Format description
-
TECH_NAME marks the beginning of a technology
specification and the name of the technology is specified
by <tech_name>
-
BEGIN_LAYER/END_LAYER mark the specification of parasitics
for one layer in the technology
-
BEGIN_VIATYPE/END_VIATYPE mark the specification of
one viatype in the technology
-
BEGIN_SUPPLIES/END_SUPPLIES mark the specification of
one or more supply voltages (in units of volts) in the design
-
each layer has a unique <layerId> specified in the
ID line ; this <layerId> should be the id of the layer used in all other
files (.pins,.topo etc.)
-
all PER-UNIT (i.e., area or length) parasitics should
be in basic units - i.e., resistance in Ohms, capacitance in Farads
and inductance in Henrys (use scientific notation as needed)
-
We use ILD_HEIGHT_{BELOW,ABOVE}, PERM_ILD_INTRALAYER
and PERM_ILD_{BELOW,ABOVE} to specify the
heights of the interlayer dielectrics to the layers above and below,
as well as the intra- (between wires of the given
layer) and inter- (between adjacent wiring layers) layer dielectric
permittivities.
-
PREFERRED_DIR optionally specifies the preferred
routing direction for the layer, and LAYER_THICKNESS specifies the
thickness of all wires on the layer.
-
<max_width> specifies the maximum allowed width
of an interconnect in this layer in database units
-
<min_width> specifies the minimum width of an
interconnect in this layer in micron units
-
<min_spacing> specified the lower bound on the
spacing between two interconnects in this layer in micron units
-
if WIRE_SIZING is DISCRETE, then WIDTHS gives a list
of usable wire widths (in micron units) in this layer to be used during
optimization ; the individual widths are separated by one or more blank
characters
-
if WIRE_SIZING is CONTINUOUS, then the CAP_TABLE
field specifies the name of the capacitance table to be used for interpolation.
We adopt the table format developed at Cadence Design Systems in 1997
(Silicon Ensemble 5.0), described in the DAC97 paper by Cong, He, Kahng, Noice, Shirali. This file defines area, fringing and coupling capacitance
values for various widths and sizing options. A linear interpolation
technique is used to find the values corresponding to any wire width and
spacing used during optimization.
-
For solvers that wish to use constant values
of per-unit (per-unit area or per-unit length) wire capacitances,
the CAP_TABLE need not be specified.
-
for a VIA, the LOWER_LAYER and UPPER_LAYER fields
specify the <layer_id> of the lower and upper layers for this via technology.
-
the VIA_RESISTANCE gives the resistance of the via
in Ohms and the VIA_CAPACITANCE gives the capacitance of the via in Farads
Format specifications
-
<layerId> is an integer
-
all lengths are specified by doubles in units
of meters
-
<r>,<c> are parasitic values and per-unit
(area or length) parasitic values are given in SI units, and are doubles
-
<w_1>,<w_2>....<w_n> are widths and sizing
options are doubles in units of meters
Device Library
For timing-driven
placement and interconnect optimization, we support simple gate
electrical models that are available in the .masters file format (via
simple methods given below for sizing), as well as more detailed
nonlinear table models available in the .timingmodels file format.
The decision as to which model to use is dependent on the solver.
-
We specify buffer/inverter characteristics
without considering the individual p/n-device parameters. We obtain
output driver on-resistance and input load capacitance from the
description of the device given in the .masters file, and obtain
values for any relative sizing of the device using scaling formulas
for both continuous as well as discrete buffer sizing. The default
scaling would be linear using the following formula.
For any size S > min_size,
R_output(S) = R_output(min_size)/S
C_input(S) = C_input(min_size) * S and
C_output(S) = C_output(min_size) * S
Note : This is only a suggested device scaling model and the
scaling of R_output and C_input/C_output
need not be linear as specified above.
QQQQQ
The simple .dev format for specifying buffer library at the gate level
is given below.
BEGIN_BUFFERLIBRARY
BUFFER <CellId>
SIZING <DISCRETE/CONTINUOUS>
MIN_SIZE <min_size>
MAX_SIZE <max_size>
SIZES <size_1> <size_2>.... <size_n>
END_BUFFERLIBRARY
Format description
-
The BUFFER statement marks the beginning each new buffer specification.
-
<buffer_name> specifies a unique name for the buffer, which is
assumed to exist as a cellId in the .masters file.
-
Information as to unateness (inverting or noninverting), input capacitance,
driver on-resistance, and intrinsic delay are all obtained from the
.masters file.
-
<min_size> specifies the minimum size of this buffer (as a double,
specifying a multiple of the size given in the .masters specification.
-
<max_size> specifies the maximum size of this buffer (as a double,
specifying a multiple of the size given in the .masters specification.
-
if SIZING is DISCRETE, then the discrete sizing choices are specified as
a list <size_1> <size_2> ... <size_n> in the SIZES field. Note
that each <size_i> is the size of the buffer as a multiple of the
size given in the .masters specification.
-
If SIZING is CONTINUOUS, then the SIZES field can be omitted and a linear
or non-linear scaling model can be used to scale the parameters for any
required size in the allowed range of sizes
Format specifications
-
<max_size>,<min_size> and <size_1>,...,<size_n> are doubles
giving sizes of the buffer as a multiple of the unit size
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