MARCO GSRC Calibrating Achievable Design: Bookshelf

GSRC Single Interconnect Tree Synthesis (Revision 1.2)

Work in progress: last updated Wed Mar 12 2003

(see other slots)

John Lillis and Milos Hrkic, Univerisity of Illinois, Chicago.
(Supported in part by the National Science Foundation under Grant No. 9875945)

Contents
 
 
I.
Introduction
II.
Data Formats
III.
Instances
IV.
Executable Solvers
V.
Relevant papers


I. Introduction

This page contains information on the single interconnect tree synthesis slot of the GSRC Bookshelf project. The page is currently evolving, and we will try to keep the page as much updated as possible. You can send your comments on this page and the file formats to the authors listed above.

Objectives

Current status

At present, we have developed the following file formats for representing the corresponding information. These are not the final versions and are expected to undergo more refinements!


II. Data Formats

The following data formats have been proposed to be used to represent information necessary for
interconnect tree synthesis. Please follow the individual links for a detailed specification and
explanation of the associated format files.
 

 Pins and Constraints

.sitspins representing pins and their location on a net and their properties

.sitslayer assigns pins to layers

.pol assigns input and output signal polarity for every pin

.cap assigns input pin capacitance

.slew assigns pins slew

.noise assigns pins noise

.rat assigns requires arrival time for every sink depending on the signal source pin

.src assigns intrinsic delay and output resistance for source pins
// eventually this will refer to .masters

.bufstat buffer stations

.bufblock represents buffer blockages

.routblock routing blockages

Topology

.topo represents a topology for a given net, allows multiple topologies

.tree represents unembedded topology tree

Target Routing Graph    // will be available soon

.trg represents a graph on which interconnect tree will be routed and embedded



 Technology  (.tech, .dev, .xdev, .res) (from Fundamental Slot)
    -- interconnect technology information for topology synthesis and optimization
    -- includes layer/via parasitics
    -- simple and complex buffer library specifications


III. Instances

To download all sample instances click here:

allnets.tar

To browse instances on net by net basis:
 

net2 All files:  net2.tar

net3 All files: net3.tar

net6 All files:  net6.tar

net9 All files:  net9.tar

net12 All files:  net12.tar

net15 All files:  net15.tar

net18 All files:  net18.tar

net24 All files:  net24.tar

routing blockages All files:  nets.routblock

buffer blockages All files:  nets.bufblock


IV. Executable solvers

Last update on Wed, Mar 12 2003. Version 2.00 Alpha. See README file first.

Buffered S-Tree

Buffered P-Tree Buffered SP-Tree Static topology buffer insertion All questions, suggestions, bug reports or interesting instances email to mhrkic@cs.uic.edu.

V. Relevant papers
 
  • John Lillis, "Algorithms for Performace Driven Design of Integrated Circuits", dissertation, UCSD 1996 ptree.pdf (851K)
  • Milos Hrkic, John Lillis, "S-Tree: A Technique for Buffered Routing Tree Synthesis", SASIMI 2001 stree.pdf (235K)
  • Milos Hrkic, John Lillis, "Buffer Tree Synthesis With Consideration of Temporal Locality, Sink Polarity Requirements, Solution Cost and Blockages", ISPD 2002 sptree.pdf (214K)