Main Memory

References:

  1. Abraham Silberschatz, Greg Gagne, and Peter Baer Galvin, "Operating System Concepts, Ninth Edition ", Chapter 8

8.1 Background

8.1.1 Basic Hardware


Figure 8.1 - A base and a limit register define a logical addresss space


Figure 8.2 - Hardware address protection with base and limit registers

8.1.2 Address Binding


Figure 8.3 - Multistep processing of a user program

8.1.3 Logical Versus Physical Address Space


Figure 8.4 - Dynamic relocation using a relocation register

8.1.4 Dynamic Loading

8.1.5 Dynamic Linking and Shared Libraries

8.2 Swapping

8.2.1 Standard Swapping


Figure 8.5 - Swapping of two processes using a disk as a backing store

8.2.2 Swapping on Mobile Systems ( New Section in 9th Edition )

8.3 Contiguous Memory Allocation

8.3.1 Memory Protection ( was Memory Mapping and Protection )


Figure 8.6 - Hardware support for relocation and limit registers

8.3.2 Memory Allocation

8.3.3. Fragmentation

8.4 Segmentation

8.4.1 Basic Method


Figure 8.7 Programmer's view of a program.


8.4.2 Segmentation Hardware


Figure 8.8 - Segmentation hardware


Figure 8.9 - Example of segmentation

8.5 Paging

8.5.1 Basic Method


Figure 8.10 - Paging hardware


Figure 8.11 - Paging model of logical and physical memory


Figure 8.12 - Paging example for a 32-byte memory with 4-byte pages


Figure 8.13 - Free frames (a) before allocation and (b) after allocation

8.5.2 Hardware Support

8.5.3 Protection


Figure 8.15 - Valid (v) or invalid (i) bit in page table

8.5.4 Shared Pages


Figure 8.16 - Sharing of code in a paging environment

8.6 Structure of the Page Table

8.6.1 Hierarchical Paging


Figure 8.17 A two-level page-table scheme


Figure 8.18 - Address translation for a two-level 32-bit paging architecture

64-bits Two-tiered leaves 42 bits in outer table

Going to a fourth level still leaves 32 bits in the outer table.

8.6.2 Hashed Page Tables


Figure 8.19 - Hashed page table

8.6.3 Inverted Page Tables


Figure 8.20 - Inverted page table

8.6.4 Oracle SPARC Solaris ( Optional, New Section in 9th Edition )

8.7 Example: Intel 32 and 64-bit Architectures ( Optional )

8.7.1.1 IA-32 Segmentation


Figure 8.21 - Logical to physical address translation in IA-32

8.7.1.1 IA-32 Segmentation


Figure 8.22 - IA-32 segmentation

8.7.1.2 IA-32 Paging


Figure 8.23 - Paging in the IA-32 architecture.


Figure 8.24 - Page address extensions.

8.7.2 x86-64


Figure 8.25 - x86-64 linear address.

8.8 Example: ARM Architecture ( Optional )


Figure 8.26 - Logical address translation in ARM.


Old 8.7.3 Linux on Pentium Systems - Omitted from the Ninth Edition

8.8 Summary