A Brief Introduction to the use of "make"

General Purpose & Usefulness

make Configuration Files

At the heart of make lies one or more configuration files, which specify what file(s) are required to build a specified target, and what commands must be executed to build that target. These configuration files lie in one of three locations:

Basic makefile Syntax

A makefile consists of a series of one or more "targets", which are the desired products of running make. For each target there is a list of dependencies and one or more command lines necessary for building the desired target. The syntax is as follows:

target : dependencies
< TAB >command line(s) to build the target
< TAB >command line(s) to build the target, ...

Note that the lines containing the necessary commands must begin with tabs, or else make will not work.


The following makefile contains information for creating "myprog" from 3 input files:

myprog : myfile1.c myfile2.c myfile.h
      cc -o myprog myfile1.c myfile2.c

In this example make will check to see if any of the three dependencies have changed since the last time "myprog" was created, and will rebuild myprog using the cc command line if necessary.


Internal Macros


Suffix Rules

Further Reading

For further information regarding make, the following text is highly reccomended: