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\title{HW2 -- Formal Memory Models}
\author{CS 554, Fall 2025\\ Due Sep. 5}
\date{}

\begin{document}
\maketitle
\section{Rules}
\subsection{SC, operational}
\begin{mathpar}
\inference[store]{\sigma_i = (\texttt{store}\ \ell\ v; \sigma_i')}{(\sigma_1 \parallel ... \ \sigma_i \ ... \parallel \sigma_n, m) \rightarrow (\sigma_1 \parallel ... \  \sigma_i' \ ... \parallel \sigma_n, m[\ell \mapsto v])}

\inference[load]{\sigma_i = (r\ \texttt{=}\ \texttt{load}\ \ell; \sigma_i')}{(\sigma_1 \parallel ... \ \sigma_i \ ... \parallel \sigma_n, m) \xrightarrow{R\;r\;m(\ell)} (\sigma_1 \parallel ... \  \sigma_i' \ ... \parallel \sigma_n, m)}
\end{mathpar}

\subsection{TSO, operational}
\begin{mathpar}
\inference[store]{\sigma_i = (\texttt{store}\ \ell\ v; s_i', b)}{(\sigma_1 \parallel ... \ \sigma_i \ ... \parallel \sigma_n, m) \rightarrow (\sigma_1 \parallel ... \  (s_i', W\;\ell\;v; b) \ ... \parallel \sigma_n, m)}

\inference[propagate]{\sigma_i = (s_i, b; W\,\ell\;v)}{(\sigma_1 \parallel ... \ \sigma_i \ ... \parallel \sigma_n, m) \rightarrow (\sigma_1 \parallel ... \  (s_i, b) \ ... \parallel \sigma_n, m[\ell \mapsto v])}

\inference[load-mem]{\sigma_i = (r\ \texttt{=}\ \texttt{load}\ \ell; s_i', b) \and W\,\ell \not\in b}{(\sigma_1 \parallel ... \ \sigma_i \ ... \parallel \sigma_n, m) \xrightarrow{R\;r\;m(\ell)} (\sigma_1 \parallel ... \  (s_i', b) \ ... \parallel \sigma_n, m)}

\inference[load-buf]{\sigma_i = (r\ \texttt{=}\ \texttt{load}\ \ell; s_i', b) \and \text{first }\ell\text{ in }b\text{ is }W\,\ell\;v}{(\sigma_1 \parallel ... \ \sigma_i \ ... \parallel \sigma_n, m) \xrightarrow{R\;r\;v} (\sigma_1 \parallel ... \  (s_i', b) \ ... \parallel \sigma_n, m)}

\inference[fence]{\sigma_i = (\texttt{fence}; s_i', \cdot)}{(\sigma_1 \parallel ... \ \sigma_i \ ... \parallel \sigma_n, m) \rightarrow (\sigma_1 \parallel ... \  (s_i', \cdot) \ ... \parallel \sigma_n, m)}
\end{mathpar}
Note that $\cdot$ means an empty list.

\subsection{SC, axiomatic}
\begin{enumerate}
\item Every operation within a thread is ordered by program order ($\mathsf{po}$).
\item There is a total order ($\mathsf{to}$) on all operations, consistent with $\mathsf{po}$.
\item Each read $R\ \ell\ v$ has the same value as the immediately preceding write to $\ell$ in $\mathsf{to}$.
\end{enumerate}

\subsection{TSO, axiomatic}
\begin{enumerate}
\item Every operation within a thread is ordered by program order ($\mathsf{po}$), \emph{except} write operations to read operations.
\item There is a total order ($\mathsf{tso}$) on all write operations, consistent with $\mathsf{po}$.
\item There is a partial read-from order ($\mathsf{rf}$) that orders a write $W\, \ell\ v$ before any reads \emph{in other threads} that read its value. Each read reads either the value of the immediately preceding write in the same thread, or the write it has an $\mathsf{rf}$ edge to.
Furthermore, for each pair of a write $W\, \ell\ v$ and a read $R\ \ell\ v$ that reads from it, there must not be another write to the same location ($W\,\ell\ v'$) ordered between them, or ordered after $W\, \ell\ v$ and earlier in the same thread as $R\ \ell\ v$. Equivalently, we can draw a from-read edge ($\mathsf{fr}$) from each read to the $\mathsf{tso}$-next write to the same location, and there are no cycles in the order $\mathsf{po}'_\ell \cup \mathsf{tso} \cup \mathsf{rf} \cup \mathsf{fr}$ (where $\mathsf{po}'_\ell$ orders all operations on $\ell$ within the same thread, \emph{including} writes to reads).
\item The combination of all of these orders ($\mathsf{po} \cup \mathsf{tso} \cup \mathsf{rf}$) is acyclic.
\end{enumerate}

\section{Problems}
This is a written homework with 3 problems, each of which has multiple parts.

\begin{enumerate}
\item Consider the following program:

\begin{tabular}{l || l}
\texttt{store(x, 1)} &\ \texttt{store(y, 1)} \\
\texttt{r1 = load(y)} &\  \texttt{r2 = load(x)}
\end{tabular}

\begin{enumerate}
\item Show a sequence of steps this program can take in the operational SC memory model, producing the outcome where \texttt{r1} is 0 and \texttt{r2} is 1.

\vspace{10em}

\item Show a sequence of steps this program can take in the operational TSO memory model, producing the outcome where \texttt{r1} is 0 and \texttt{r2} is 1.
\vspace{10em}

\item Draw an execution graph for the axiomatic SC model that justifies the outcome where \texttt{r1} is 0 and \texttt{r2} is 1.

\vspace{20em}

\item Draw an execution graph for the axiomatic TSO model that justifies the outcome where \texttt{r1} is 0 and \texttt{r2} is 1.

\vspace{16em}

\end{enumerate}

\newpage
\item Suppose we changed the operational TSO model's load-mem rule to remove the requirement $W\, \ell \not\in b$.
\begin{enumerate}
\item Intuitively, how would this change the behavior of the machine?

\vspace{12em}

\item Write a concrete program where this change would be visible---i.e., one that can have an outcome under the changed model that isn't possible under the real TSO model.

\vspace{12em}

\end{enumerate}

\newpage
\item Suppose we changed the axiomatic TSO model to remove the ``no intervening write'' condition and the $\mathsf{fr}$ edges, i.e., we changed rule 3 to simply ``There is a partial read-from order ($\mathsf{rf}$) that orders a write $W\, \ell\ v$ before any reads in other threads that read its value. Each read reads either the value of the immediately preceding write in the same thread, or the write it has an $\mathsf{rf}$ edge to.''
\begin{enumerate}
\item Intuitively, how would this change the behavior of the model?

\vspace{12em}

\item Write a concrete program where this change would be visible---i.e., one that can have an outcome under the changed model that isn't possible under the real TSO model.

\vspace{12em}

\item Can you think of a way to make the same change to the operational TSO model? Or, can you explain why it would be impossible to make such a change? (This will be very generously graded---just write out your thoughts.)
\end{enumerate}

\end{enumerate}

\end{document}