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The generic disassembler, produces symbolic relocatable disassembly of an object file in Executable and Linking Format (ELF). It uses a processor model that contains instruction set description of the processors in a language called Sim-nML. Sim-nML is a simple, elegant and powerful language to express the behavior of processors at instruction level. It uses synthesized attributes to represent timing information, instruction semantics, assembly language syntax and binary representation of instructions. Generic Disassembler facilitates disassembly of programs in a GNU-compatible format. For identifying the instructions, Depth First Search (DFS) and backtracking is used on a tree like structure of the Sim-nML instruction set description. Since the attributes of an instruction are scattered in various subtrees, syntax for the instruction is collected from the subtrees i selected during traversal. Different parts of a single instruction may be matched with different subtrees. Symbolic and relocatable disassembly is achieved by using relocation and symbol information from the object file and analyzing the code to identify basic blocks.

Conclusion/Results The Generic Disassembler was tested for PowerPC603, Motorola68HC11, and MIPS R10000 processor models. Produced output was compatible to GNU assemblers. In the output produced by GCC redundant labels are generated that are not referred to by any instruction. All such labels were not generated by the generic disassembler.