// Scott Price
// CS366 Program 5
// Nov. 29, 2004
//
// Microcode implementing the following instructions: 
//				 22) MOVEI ( movei rj, ri)  // rj <- ri
// 
// 				 63) EXT  ( ext )		    // enter into extended opcode mode, where a third instruction byte specifies
//								            // which extended instruction to select, starting at jump table address 64
//               64) INCN ( incn ri, n)   	// ri <- ri + n, where n is IR_CONST8
//               65) SUBN ( incn ri, n)   	// ri <- ri - n, where n is IR_CONST8
//
// NOTE: This file also contains the code for all previous microcode programs
//
// ucode file
// Register usage convention:
// r0..r3  Assembler use by user
// r4	   ucode internal use
// r5  	   stack pointer (sp)
// r6      used for PC increment for implementing branching, also as a temporary register
// r7	   used as the PC
// -------------------------- Fetch Section ---------------------
fetch0: 	a_sel=7, b_sel=7, alu_sel=AND, r6_write, mar_sel=LOAD;
fetch1: 	r7_write, a_sel=6, alu_sel=ADDA, c_in, read, ir0_sel=LOAD, if wait then goto fetch1 endif;
fetch2: 	a_sel=7, b_sel=7, alu_sel=AND, r6_write, mar_sel=LOAD;
fetch3:		r7_write, a_sel=6, alu_sel=ADDA, c_in, read, ir1_sel=LOAD, if wait then goto fetch3 endif;
                goto opcode[IR_OPCODE];


// ------------------- Opcode Jump Table Section -----------------
//@nop
// 0) NO_OP
opcode[0]: 	goto fetch0;
	
//@add ri, rj, rk
// 1) ADD (ri <- rj + rk)
opcode[1]: 	ri_sel, rj_sel, rk_sel, alu_sel=ADD, goto fetch0; 
		
//@li ri, ir_const8
// 2) LOAD_IMMEDIATE (ri <- ir_const8)
opcode[2]: 	result_sel=IR_CONST8, ri_sel, goto fetch0;                  		

//@bz rj, ir_const4
// 3) BR_IF_ZERO (bz rj, ir_const4)
opcode[3]: 	rj_sel, alu_sel=SUBA, r6_write, result_sel=IR_CONST4, 
			if c_out then goto fetch0 else goto branch endif;

//@bnz rj, ir_const4
// 4) BR_IF_NOT_ZERO (bnz rj, ir_const4)
opcode[4]: 	rj_sel, alu_sel=SUBA, r6_write, result_sel=IR_CONST4, 
			if c_out then goto branch else goto fetch0 endif;

//@jump ir_const8
// 5) JUMP (jump ir_const8)
opcode[5]: 	a_sel=0, b_sel=0, alu_sel=AND, r6_write, result_sel=IR_CONST8, goto branch;       

//@move ri, rj
// 6) MOVE (ri <- rj)
opcode[6]: 	ri_sel, rj_sel, alu_sel=ADDA, goto fetch0;    	

//@sb rj, rk
// 7) STORE_BYTE (mem[rj] <= rk)
opcode[7]:	rj_sel, alu_sel=ADDA, mar_sel=LOAD, goto opcode7.1;	

//@lb ri, rj
// 8) LOAD_BYTE (ri <- mem[rj])
opcode[8]: 	rj_sel, alu_sel=ADDA, mar_sel=LOAD, goto memread; 	

//@rs ri, rj
// 9) RIGHT_SHIFT ri << (rj>>1)  
opcode[9]: 	rj_sel, r6_write, alu_sel=ADDA, goto opcode9.1;   // Store rj into r6   	

//@sub ri, rj, rk
// 10) SUB (ri <- rj - rk)
opcode[10]: 	ri_sel, rj_sel, rk_sel, c_in, alu_sel=SUB, goto fetch0; 		
	
//@halt
// 11) HALT
opcode[11]: 	goto opcode[11];  	

//@blez rj, ir_const4
// 12) BR_IF_LESS_OR_EQUAL_ZERO (blez rj, ir_const4)  
opcode[12]:	rj_sel, alu_sel=SUBA, r6_write, result_sel=IR_CONST4, 
		if c_out then goto opcode12.1 else goto branch endif;

//@inca ri, rj
// 13) INCA  ( ri <- ++ri)  
opcode[13]: goto fetch0;

//@incb ri, rj
// 14) INCB  ( rj <- ++rj)   // ri == rj in mem file instruction
opcode[14]: ri_sel, rj_sel, alu_sel = ADDA, c_in, goto fetch0; 	// write to ri, select from rj, ADDA with c_in so rj actually is incremented.

//@setsp ir_const8
// 15) SETSP ( setsp n)		// sp <- n, assume sp is r5, n is from IR_CONST8
opcode[15]: r5_write, result_sel = IR_CONST8, goto fetch0; 		// r5 = sp, so write to r5 and get from IR_CONST8.

//@load ri, n(sp)
// 16) LOAD ( load ri, n(sp) )	// ri <- Mem[ sp + n]	// assume sp is r5, n is from IR_CONST8
opcode[16]: r4_write, result_sel = IR_CONST8, goto opcode16.1;	// Store IR_CONST8 in r4, go to extra instructions.

//@store n(sp), rj
// 17) STORE ( store( n(sp), rj)	// Mem[ sp + n] <- rj	// assume sp is r5, n is from IR_CONST4
opcode[17]: r4_write, result_sel = IR_CONST4, goto opcode17.1;	// Store IR_CONST4 in r4, go to extra instructions.

//@addm ri, a[3]
// 18) ADDM ( addm ri, n)  		// ri <- rj + Mem[ n], where n is CONST8 from the third instruction byte //      ri == rj in the mem file instruction
opcode[18]: a_sel=7, alu_sel=ADDA, mar_sel=LOAD, goto opcode18.1; //Since r7 already has the address of the 3rd byte, pass it through the ALU to the MAR

//@addms a[5], rj, rk
// 19) ADDMS ( addms n, rj, rk)   // Mem[ n] <- rj + rk, where n is CONST8 from the third instruction byte
opcode[19]: rj_sel, rk_sel, alu_sel=ADD, mdr_sel=LOAD_ALU, goto opcode19.1; //Add rj and rk and store their sum in the MDR

//@add2m ri, a[3], b[4]
//20) ADD2M ( add2m ri, n, p)  	// ri <- Mem[ n] + Mem[ p], where n is CONST8 from the third instruction byte //     and p is is CONST8 from the fourth instruction byte
opcode[20]: a_sel=7, alu_sel=ADDA, mar_sel=LOAD, goto opcode20.1; //Since r7 already has the address of the 3rd byte, pass it through the ALU to the MAR

//@add2ms a[3], b[4], c[5]
//21) ADD2MS (add2ms r, n, p)	// Mem[ r] <- Mem[ n] + Mem[ p],where n is CONST8 from the third instruction byte //     and p is is CONST8 from the fourth instruction byte//     and r is is CONST8 from the fifth instruction byte								//     and p is is CONST8 from the fourth instruction byte
opcode[21]: a_sel=7, alu_sel=ADDA, mar_sel=LOAD, goto opcode21.1; //Since r7 already has the address of the 3rd byte, pass it through the ALU to the MAR

//@movei rj, ri
//22) MOVEI ( movei rj, ri)  // rj <- ri
opcode[22]: a_sel=6, alu_sel=ADDA, mar_sel=LOAD, goto opcode22.1; // Going to process the ri part first, so load it's address

//@23
opcode[23]: goto fetch0;
//@24
opcode[24]: goto fetch0;
//@25
opcode[25]: goto fetch0;
//@26
opcode[26]: goto fetch0;
//@27
opcode[27]: goto fetch0;
//@28
opcode[28]: goto fetch0;
//@29
opcode[29]: goto fetch0;
//@30
opcode[30]: goto fetch0;
//@31
opcode[31]: goto fetch0;
//@32
opcode[32]: goto fetch0;
//@33
opcode[33]: goto fetch0;
//@34
opcode[34]: goto fetch0;
//@35
opcode[35]: goto fetch0;
//@36
opcode[36]: goto fetch0;
//@37
opcode[37]: goto fetch0;
//@38
opcode[38]: goto fetch0;
//@39
opcode[39]: goto fetch0;
//@40
opcode[40]: goto fetch0;
//@41
opcode[41]: goto fetch0;
//@42
opcode[42]: goto fetch0;
//@43
opcode[43]: goto fetch0;
//@44
opcode[44]: goto fetch0;
//@45
opcode[45]: goto fetch0;
//@46
opcode[46]: goto fetch0;
//@47
opcode[47]: goto fetch0;
//@48
opcode[48]: goto fetch0;
//@49
opcode[49]: goto fetch0;
//@50
opcode[50]: goto fetch0;
//@51
opcode[51]: goto fetch0;
//@52
opcode[52]: goto fetch0;
//@53
opcode[53]: goto fetch0;
//@54
opcode[54]: goto fetch0;
//@55
opcode[55]: goto fetch0;
//@56
opcode[56]: goto fetch0;
//@57
opcode[57]: goto fetch0;
//@58
opcode[58]: goto fetch0;
//@59
opcode[59]: goto fetch0;
//@60
opcode[60]: goto fetch0;
//@61
opcode[61]: goto fetch0;
//@62
opcode[62]: goto fetch0;

//@ext a[3]
//63) EXT  ( ext )			// enter into extended opcode mode, where a third instruction byte specifies // which extended instruction to select, starting at jump table address 65
opcode[63]: a_sel=7, alu_sel=ADDA, mar_sel=LOAD, goto opcode63.1; // Load address of the third instruction byte, then goto the rest of the instruction

// ------------------ Extended Instruction Section --------------------
		// implement branch by adding offset (r6) to PC (r7)
branch:    	r7_write, a_sel=7, b_sel=6, alu_sel=ADD, goto fetch0;

		// Continuation of 7) STORE_BYTE (mem[rj] <= rk)
opcode7.1: 	a_sel=5, b_sel=5, alu_sel=SUB, c_in, r5_write;
		rk_sel, a_sel=5, alu_sel=OR, mdr_sel=LOAD_ALU;
memwrite:		write, if wait then goto memwrite else goto fetch0 endif;

		// Continuation of 8) LOAD_BYTE (ri <- mem[rj])
memread: read, mdr_sel=LOAD_MEM, if wait then goto memread endif;
		result_sel=MDR, ri_sel, goto fetch0;

		// Continuation of 9) RIGHT_SHIFT ri << (rj>>1).
		// Shift right by doing circular shift left 7 times
opcode9.1: 	r5_write, r4_write, a_sel=4, b_sel=4, alu_sel=SUB, c_in; // r4 <- 0, r5 <- 0
		// Store constant 7 (111) in r4 to use as a counter
		r4_write, a_sel=4, b_sel = 4, alu_sel=ADD, c_in;  // r4 <- 1
		r4_write, a_sel=4, b_sel = 4, alu_sel=ADD, c_in;  // r4 <- 11
		r4_write, a_sel=4, b_sel = 4, alu_sel=ADD, c_in;  // r4 <- 111
		// r4--, check if r4 is zero
shiftLoop:	r4_write, a_sel=4, alu_sel=SUBA, 
			if c_out then goto notZero endif;  
		// r4==0, so store result in ri 
		ri_sel, a_sel=5, alu_sel=ADDA, goto fetch0;	// ri <- r5;  
		// now left shift r6 by adding to itself and check c_out 
notZero:  	r6_write, a_sel=6, b_sel=6, alu_sel=ADD, if c_out then goto carry1 else goto carry0 endif;
carry1:  		r5_write, a_sel=5, b_sel=5, alu_sel=ADD, c_in, goto shiftLoop;  // shift in a 1 to right of r5
carry0:  		r5_write, a_sel=5, b_sel=5, alu_sel=ADD, goto shiftLoop;    // shift in a 0 to the right of r5

		// Continuation of: 12) BR_IF_LESS_OR_EQUAL_ZERO (blez rj, ir_const4)  
		// pass rj through ALU and check to see if it is negative
opcode12.1:	rj_sel, alu_sel=ADDA, r6_write, result_sel=IR_CONST4, 
			if m_7 then goto branch else goto fetch0 endif;

		// Continuation of: 16) LOAD ( load ri, n(sp) )	// ri <- Mem[ sp + n]	// assume sp is r5, n is from IR_CONST8
opcode16.1: a_sel = 4, b_sel = 5, alu_sel = ADD, mar_sel=LOAD, goto memread;	// add r4 and r5, store address in mar. Now, go to memread to do the actual read.
		
		// Continuation of: 17) STORE ( store( n(sp), rj)	// Mem[ sp + n] <- rj	// assume sp is r5, n is from IR_CONST4
opcode17.1: r4_write, a_sel = 4, b_sel = 5, alu_sel = add, mar_sel=LOAD;	// add r4 and r5, store back in r4 and in mar.
			rj_sel, alu_sel = ADDA, mdr_sel = LOAD_ALU, goto memwrite;		// pass rj through ALU and store in mdr. Now goto memwrite to do the actual write.

			// Continuation of: // 18) ADDM ( addm ri, n)  		 ri <- rj + Mem[ n], where n is CONST8 from the third instruction byte //							     ri == rj in the mem file instruction
opcode18.1: read, mdr_sel=LOAD_MEM, if wait then goto opcode18.1 endif;	// Read CONST8 from third inst. byte
			result_sel = MDR, r4_write; // Store the const8 value in r4 
			a_sel=4, alu_sel = ADDA, mar_sel=LOAD; // pass r4 through ALU and store in MAR
opcode18.2:	read, mdr_sel=LOAD_MEM, if wait then goto opcode18.2 endif; //Get value in memory
			r4_write, result_sel = MDR; //store the memory value in r4 	       
			ri_sel, rj_sel, b_sel = 4, alu_sel = ADD; //do the operation now that everything is completed and in the right place(registers)			
			r7_write, a_sel=7, alu_sel=ADDA, c_in; //Increment r7, the PC
			goto fetch0; //go back up to fetch0;
			
		// Continuation of: // 19) ADDMS ( addms n, rj, rk)   // Mem[ n] <- rj + rk, where n is CONST8 from the third instruction byte
opcode19.1:	a_sel=7, alu_sel=ADDA, mar_sel=LOAD; //Since r7 is already pointing at the 3rd byte, pass it through the ALU and store it in the MAR
opcode19.2:	read, ir0_sel=LOAD, if wait then goto opcode19.2 endif; //do the read and store it in IR0
			result_sel = IR_CONST8, r4_write;	// store the const value in r4
			a_sel=4, alu_sel=ADDA, mar_sel=LOAD; //pass r4 through the ALU to the MAR
opcode19.3: write, if wait then goto opcode19.3 endif; // do the write			
			r7_write, a_sel=7, alu_sel=ADDA, c_in; //Increment r7, the PC
			goto fetch0; //go back up to fetch0;

		// Coninuation of: // 20) ADD2M ( add2m ri, n, p)  	// ri <- Mem[ n] + Mem[ p], where n is CONST8 from the third instruction byte //     and p is is CONST8 from the fourth instruction byte	
opcode20.1: read, ir0_sel=LOAD, if wait then goto opcode20.1 endif; //do the read, and store it into IR0
			r4_write, result_sel=IR_CONST8;	// write the const to r4 
			a_sel=4, alu_sel=ADDA, mar_sel=LOAD;			// pass r4 through the ALU and store it into the MAR
opcode20.2:	read, mdr_sel=LOAD_MEM, if wait then goto opcode20.2 endif;	//do the read
			r4_write, result_sel=MDR;	//store the memory value in r4
			a_sel=7, alu_sel=ADDA, c_in, mar_sel=LOAD;	//Increment r7 by one, and store the new value in MAR
opcode20.3:	read, ir0_sel=LOAD, if wait then goto opcode20.3 endif;	//do the read and store it in IR0
			r6_write, result_sel=IR_CONST8, alu_sel=ADDA;	//write the const to r6
			a_sel=6, mar_sel=LOAD, alu_sel=ADDA; // pass r6 through the ALU and store it into the MAR
opcode20.4:	read, mdr_sel=LOAD_MEM, if wait then goto opcode20.4 endif; // do the read
			r6_write, result_sel=MDR, alu_sel=ADDA; //store the memory value in r6
			ri_sel, a_sel=4, b_sel=6, alu_sel=ADD;	// do the addition of r4 + r6 and store it in ri
			r7_write, a_sel=7, alu_sel=ADDA, c_in; // increment r7
			r7_write, a_sel=7, alu_sel=ADDA, c_in; // increment r7
			goto fetch0; //go back up to fetch0
			
		// Continuation of: 21) ADD2MS (add2ms r, n, p)	// Mem[ r] <- Mem[ n] + Mem[ p],where n is CONST8 from the third instruction byte//     and p is is CONST8 from the fourth instruction byte//     and r is is CONST8 from the fifth instruction byte								//     and p is is CONST8 from the fourth instruction byte
opcode21.1:	read, ir0_sel=LOAD, if wait then goto opcode21.1 endif; //do the read and store it in IR0
			r4_write, result_sel=IR_CONST8; //store the const value in r4
			a_sel=4, alu_sel=ADDA, mar_sel=LOAD; //pass r4 through ALU into MAR
opcode21.2:	read, mdr_sel=LOAD_MEM, if wait then goto opcode21.2 endif; //do the read
			r4_write, result_sel=MDR; // store the memory value in r4
			a_sel=7, alu_sel=ADDA, c_in, mar_sel=LOAD; //increment r7 and store result in MAR
opcode21.3:	read, ir0_sel=LOAD, if wait then goto opcode21.3 endif; //do the read
			r6_write, result_sel=IR_CONST8; // store the const in r6
			a_sel=6, mar_sel=LOAD, alu_sel=ADDA; // pass r6 through the ALU and store in MAR
opcode21.4:	read, mdr_sel=LOAD_MEM, if wait then goto opcode21.4 endif; // do the read
			r6_write, result_sel=MDR; //store memory value in r6
			a_sel=4, b_sel=6, alu_sel=ADD, mdr_sel=LOAD_ALU; //do the addition and store in MDR and r6
			r7_write, a_sel=7, alu_sel=ADDA, c_in; // increment r7
			r7_write, a_sel=7, alu_sel=ADDA, c_in, mar_sel=LOAD; // increment r7 (so that it points to the 5th byte) and store it in MAR		
opcode21.5: read, ir0_sel=LOAD, if wait then goto opcode21.5 endif; //do the read and store it int IR0 
			r4_write, result_sel=IR_CONST8;	//store the const value in r4
			a_sel=4, mar_sel=LOAD, alu_sel=ADDA; // pass r4 through the ALU to the MAR
opcode21.6: write, if wait then goto opcode21.6 endif; //do the write
			r7_write, a_sel=7, alu_sel=ADDA, c_in; //increment r7 so it points to the first line of the next instruction
			goto fetch0; //go back up to fetch0
			
		// Continuation of: 22) MOVEI ( movei rj, ri)  // rj <- ri
opcode22.1: read, mdr_sel=LOAD_MEM, if wait then goto opcode22.1 endif; //do the read and store it in MDR		
            r4_write, result_sel=MDR; //stick the value in r4
			r6_write, a_sel=6, b_sel=6, alu_sel=SUB, c_in; //r6 <- 0          
			//Need to get rid of the opcode part of the ri byte, so need to load a masking value           
			r6_write, a_sel=6, alu_sel=ADDA, c_in; // r6 <- 1
			r6_write, a_sel=6, alu_sel=ADDA, c_in; // r6 <- 10
			r6_write, a_sel=6, alu_sel=ADDA, c_in; // r6 <- 11
			r4_write, a_sel=4, b_sel=6, alu_sel=AND; // r4 now will just have the ri bits, store it in r4 again
			//now r4 has just the ri value in the rightmost two bits, so i need to add it to itself 6 times to get those bits into the rj position
			r4_write, a_sel=4, b_sel=4, alu_sel=ADD; // add 1
			r4_write, a_sel=4, b_sel=4, alu_sel=ADD; // add 2
			r4_write, a_sel=4, b_sel=4, alu_sel=ADD; // add 3
			r4_write, a_sel=4, b_sel=4, alu_sel=ADD; // add 4
			r4_write, a_sel=4, b_sel=4, alu_sel=ADD; // add 5
			mdr_sel=LOAD_ALU, a_sel=4, b_sel=4, alu_sel=ADD; // add 6 and store in mdr since it's done
			//Now I need to get the address into MAR of the first instruction byte, so we need to subtract from r7 twice
			r6_write, a_sel=7, alu_sel=SUBA; //subtract from r7 and store in r6
			mar_sel=LOAD, a_sel=6, alu_sel=SUBA; //subtract from r6 and store in MAR
opcode22.2: write, if wait then goto opcode22.2 endif; //do the write
			r4_write, result_sel=IR_CONST8; // store the original const8 in r4
			//now r4 has the rj bits that we need to right shift to make it occupy the ri bits		
			//Since we need to use r5 for right shifting, I'll store the r5(sp) in the MDR now, and then reload it after the right shift
			a_sel=5, alu_sel=ADDA, mdr_sel=LOAD_ALU; //store r5 in mdr so I can use r5
			//The following code is right shift code from above, slightly modified
			a_sel=4, r6_write, alu_sel=ADDA;   // Store rj into r6
			r5_write, r4_write, a_sel=4, b_sel=4, alu_sel=SUB, c_in; // r4 <- 0, r5 <- 0
		    // Store constant 7 (111) in r4 to use as a counter
		 	r4_write, a_sel=4, b_sel = 4, alu_sel=ADD, c_in;  // r4 <- 1
			r4_write, a_sel=4, b_sel = 4, alu_sel=ADD;  // r4 <- 10			
			// r4--, check if r4 is zero	
shiftLoop22:  r4_write, a_sel=4, alu_sel=SUBA, 
		    if c_out then goto notZero22 endif;  
		    // r4==0, so store result in ri 
		    r6_write, a_sel=5, alu_sel=ADDA, goto rshiftdone;	// r6 <- r5;
		    // now left shift r6 by adding to itself and check c_out 
notZero22:  r6_write, a_sel=6, b_sel=6, alu_sel=ADD, if c_out then goto carry122 else goto carry022 endif;
carry122:  	r5_write, a_sel=5, b_sel=5, alu_sel=ADD, c_in, goto shiftLoop22;  // shift in a 1 to right of r5
carry022:  	r5_write, a_sel=5, b_sel=5, alu_sel=ADD, goto shiftLoop22;    // shift in a 0 to the right of r5
rshiftdone: result_sel=MDR, r5_write; // restore r5;
			a_sel=6, alu_sel=ADDA, mdr_sel=LOAD_ALU; //store the value in the MDR
			mar_sel=LOAD, a_sel=7, alu_sel=SUBA; //load the address of the second byte into the MAR
opcode22.3: write, if wait then goto opcode22.3 endif;
			r6_write, a_sel=7, alu_sel=SUBA; //get the addresses again to read
			mar_sel=LOAD, a_sel=6, alu_sel=SUBA; //address of the first byte
opcode22.4: ir0_sel=LOAD, read, if wait then goto opcode22.4 endif; //do the read
			mar_sel=LOAD, a_sel=6, alu_sel=ADDA; //address of the second byte
opcode22.5: ir1_sel=LOAD, read, if wait then goto opcode22.5 endif; //do the read
			ri_sel, rj_sel, alu_sel=ADDA; //ri <- rj
			goto fetch0; //Go back to fetch0

		// Continuation of: // 63) EXT  ( ext )			// enter into extended opcode mode, where a third instruction byte specifies // which extended instruction to select, starting at jump table address 65			
opcode63.1: mdr_sel=LOAD_MEM, read, if wait then goto opcode63.1 endif; // do the read
			r4_write, result_sel=MDR; // stick the extended opcode in r4
			//r4 will contain a number >= 64, so in order to figure out which number it is, i'll first subtract 64
			//from the number and then decrement it. When m7 goes hi it means r4 was 0, so jump to the appropriate instruction
			r6_write, a_sel=6, b_sel=6, alu_sel=SUB, c_in; // r6 <- 0
			r6_write, a_sel=6, b_sel=6, c_in, alu_sel=ADD; //need 64 so start to fill r6 with ones
			r6_write, a_sel=6, b_sel=6, alu_sel=ADD; //need 64 so start to fill r6 with ones
			r6_write, a_sel=6, b_sel=6, alu_sel=ADD; //need 64 so start to fill r6 with ones
			r6_write, a_sel=6, b_sel=6, alu_sel=ADD; //need 64 so start to fill r6 with ones
			r6_write, a_sel=6, b_sel=6, alu_sel=ADD; //need 64 so start to fill r6 with ones
			r6_write, a_sel=6, b_sel=6, alu_sel=ADD; //need 64 so start to fill r6 with ones
			r6_write, a_sel=6, b_sel=6, alu_sel=ADD; //need 64 so start to fill r6 with ones
			r4_write, a_sel=4, b_sel=6, alu_sel=SUB, c_in; //Do the subraction to get rid of the offset
			r4_write, a_sel=4, alu_sel=SUBA, if m_7 then goto opcode64 endif; //If v happens then r4 was 0, thus it was originally 64, so goto opcode 64
			r4_write, a_sel=4, alu_sel=SUBA, if m_7 then goto opcode65 endif; //If v happens now, it was 0, but it already was decremented so it was originally 1 (+64) so goto opcode 65

// ------------------ Extended Extended Instruction Section --------------------

//@incn,64,8.3
// 64) INCN (incn ri, n) ri <- ri + n
opcode64:   a_sel=7, alu_sel=SUBA, mar_sel=LOAD; // Going to process the ri part first, so load it's address   
opcode64.1: read, mdr_sel=LOAD_MEM, if wait then goto opcode64.1 endif; //do the read and store it in MDR		
            r4_write, result_sel=MDR; //stick the value in r4
			r6_write, a_sel=6, b_sel=6, alu_sel=SUB, c_in; //r6 <- 0          
			//Need to get rid of the opcode part of the ri byte, so need to load a masking value           
			r6_write, a_sel=6, alu_sel=ADDA, c_in; // r6 <- 1
			r6_write, a_sel=6, alu_sel=ADDA, c_in; // r6 <- 10
			r6_write, a_sel=6, alu_sel=ADDA, c_in; // r6 <- 11
			r4_write, a_sel=4, b_sel=6, alu_sel=AND; // r4 now will just have the ri bits, store it in MDR, as it will be written back to memory soon
			//now r4 has just the ri value in the rightmost two bits, so i need to add it to itself 7 times to get those bits into the rj position
			r4_write, a_sel=4, b_sel=4, alu_sel=ADD; // add 1
			r4_write, a_sel=4, b_sel=4, alu_sel=ADD; // add 2
			r4_write, a_sel=4, b_sel=4, alu_sel=ADD; // add 3
			r4_write, a_sel=4, b_sel=4, alu_sel=ADD; // add 4
			r4_write, a_sel=4, b_sel=4, alu_sel=ADD; // add 5
			mdr_sel=LOAD_ALU, a_sel=4, b_sel=4, alu_sel=ADD; // add 6 and store in mdr since it's done
			r6_write, a_sel=7, alu_sel=SUBA; //subtract from r7 and store in r6
			mar_sel=LOAD, a_sel=6, alu_sel=SUBA; //subtract from r6 and store in MAR
opcode64.2: write, if wait then goto opcode64.2 endif; //do the write
			r4_write, result_sel=IR_CONST8; // store the const in r4
			a_sel=6, alu_sel=SUBA, mar_sel=LOAD; //store the address of the rj byte in the mar
opcode64.3: ir0_sel=LOAD, read, if wait then goto opcode64.3 endif; //read and store it in ir0
			rj_sel, b_sel=4, alu_sel=ADD, ri_sel; // do the addition and store back in ri
			r7_write, a_sel=7, alu_sel=ADDA, c_in; // increment the PC
			goto fetch0; //go back to fetch0
			
// 65) SUBN ( incn ri, n)   	// ri <- ri - n, where n is IR_CONST8
opcode65:   a_sel=7, alu_sel=SUBA, mar_sel=LOAD; // Going to process the ri part first, so load it's address   
opcode65.1: read, mdr_sel=LOAD_MEM, if wait then goto opcode65.1 endif; //do the read and store it in MDR		
            r4_write, result_sel=MDR; //stick the value in r4
			r6_write, a_sel=6, b_sel=6, alu_sel=SUB, c_in; //r6 <- 0          
			//Need to get rid of the opcode part of the ri byte, so need to load a masking value           
			r6_write, a_sel=6, alu_sel=ADDA, c_in; // r6 <- 1
			r6_write, a_sel=6, alu_sel=ADDA, c_in; // r6 <- 10
			r6_write, a_sel=6, alu_sel=ADDA, c_in; // r6 <- 11
			r4_write, a_sel=4, b_sel=6, alu_sel=AND; // r4 now will just have the ri bits, store it in MDR, as it will be written back to memory soon
			//now r4 has just the ri value in the rightmost two bits, so i need to add it to itself 7 times to get those bits into the rj position
			r4_write, a_sel=4, b_sel=4, alu_sel=ADD; // add 1
			r4_write, a_sel=4, b_sel=4, alu_sel=ADD; // add 2
			r4_write, a_sel=4, b_sel=4, alu_sel=ADD; // add 3
			r4_write, a_sel=4, b_sel=4, alu_sel=ADD; // add 4
			r4_write, a_sel=4, b_sel=4, alu_sel=ADD; // add 5
			mdr_sel=LOAD_ALU, a_sel=4, b_sel=4, alu_sel=ADD; // add 6 and store in mdr since it's done
			r6_write, a_sel=7, alu_sel=SUBA; //subtract from r7 and store in r6
			mar_sel=LOAD, a_sel=6, alu_sel=SUBA; //subtract from r6 and store in MAR
opcode65.2: write, if wait then goto opcode65.2 endif; //do the write
			r4_write, result_sel=IR_CONST8; // store the const in r4
			a_sel=6, alu_sel=SUBA, mar_sel=LOAD; //store the address of the rj byte in the mar
opcode65.3: ir0_sel=LOAD, read, if wait then goto opcode65.3 endif; //read and store it in ir0
			rj_sel, b_sel=4, alu_sel=SUB, c_in, ri_sel; // do the subtraction and store back in ri
			r7_write, a_sel=7, alu_sel=ADDA, c_in; // increment the PC
			goto fetch0; //go back to fetch0