Assignment 6

Due: Wednesday, 11/28/2001

1. Assume the following instructions are stored in a scoreboard:

LD F0, 34(r2) // #1

LD F2, 12(r4) // #2

ADDD F4, F2, F8 // #3

MULTD F6, F2, F0 // #4

ADDD F10, F0, F10 // #5

DIVD F8, F2, F12 // #6

SUBD F2, F4, F6 // #7

MULTD F4, F12, F10 // #8

ADDD F8, F12, F10 // #9

Show the Instruction Status table, the Functional Unit Status table and the Register Result Status table (see pp. 247-249) for the above scoreboard at the time when Statement #2, #7 and #9 are read to go into the write-back state (you will need three separate tables). Use the same assumptions as used in the example on page 248, which include the latencies for the floating point units: ADDD/SUBD is 2 clock cycles, MULTD is 10 clock cycles and DIVD is 40 clock cycles.

2. Assume that a memory access when a value is in cache is one machine cycle. If the value is in main memory, the memory access time is 8 machine cycles. Assuming that a value is in cache 90% of the time, what is the average memory access time for the following two types of memory systems?

Type 1: When the value is not in the cache, the access to main memory doesn't begin until after the cache access is known to be a miss.

Type 2: When the value is not is cache, the access to main memory begins at the same time as the access to cache.

3. Use the following table to give the trace information for the cache simulations in questions 1 - 5. The first three columns hold the address of the memory access. The fourth column is to indicate if the memory access is a read of a write. The information for the first four columns will be given in the question. The fifth columns indicates which block within the set will be used to store the value. The sixth column is used to indicate whether a hit or miss occurred during the access. The seventh column should show the tag of the element stored in the block prior to the memory access (note: the tag could be empty). The last two columns are used to indicate if the memory access causes a cache block to be emptied and whether a write is required during the emptying of the cache block. When a set is not full, fill in the lowest numbered block first.

|       Address		| r/w || block | hit/ | previous | purge | write 
| Tag  | Index | Offset	|     ||       | miss |	tag	 |	 | back
|------|-------|--------|-----||-------|------|----------|-------|-------
|      |       |        |     ||       |      |          |       |

3a. For the following addresses, give the trace information for a cache simulation. The cache contains 8 blocks. Each block is 2 words long. A replacement policy of LRU with write-back is used and direct mapping scheme is used. The addresses are given as binary values followed by an "r" to indicate a read or a "w" to indicate a write.

11100011r, 11100001w, 11100010w, 10101101w, 11000010r, 11100010r, 11000000w, 10010011r, 10000010r, 11100000r, 11100010r, 10001010w, 10101010w, 10001000r

3b. For the same addresses from question 3a, give the trace information for a cache simulation. The cache contains 8 blocks. Each block is 2 words long. A replacement policy of LRU with write-back is used and fully associative mapping scheme is used.

3c. For the same addresses from question 3a, give the trace information for a cache simulation. The cache contains 8 blocks. Each block is 2 words long. A replacement policy of LRU with write-back is used and 2-way set associative mapping scheme is used.

3d. For the same addresses from question 3a, give the trace information for a cache simulation. The cache contains 8 blocks. Each block is 4 words long. A replacement policy of First-In-First-Out with write-through is used and 4-way set associative mapping scheme is used.

3e. For the same addresses from question 3a, give the trace information for a cache simulation. The cache contains 8 blocks. Each block is 1 word long. A replacement policy of First-In-First-Out with write-through is used and 2-way set associative mapping scheme is used.