1. ISSUE READ EXECUTE WRITE 1. LD F0, 34( r2) X X X X 2. LD F2, 12(r4) X X X 3. ADDD F4,F2,F8 X 4. MULTD F6,F2, F0 X 5. ADDD F10, F0, F10 6. DIVD F8,F2,F12 7. SUBD F2, F4, F6 8. MULTD F4,F12, F10 9. ADDD F8, F12, F10 1. stall the instruction in issues stage if an instruction has a same destination register or structural hazard with an earlier instruction. In this example, instruction 5 has structural hazard with 3. Hence stall it. Instr 8 has destination register as F4, same as that of instr 3. Hence stall it. Similiar reasoning applies for other instrs. 2. Stall the instr. in read stage if an instruction's one of the source register is a destination register for an earlier active instruction. Instr 3 has F2 has one of it's source reg. which is a destination reg. for instr2. Hence stall it. Same reasoning for instr4. 3. Stall the instr in write stage if the instruction writes to a register which is a source register for an earlier active instruction. No such case in this example. The case might arise in case 2 of the problem 1. ( It would be easier if you use time cycles in the above table rather than just X ) Now construct the other two tables Unit Busy OP Fi Fj Fk Qj Qk Rj Rk Integer Yes LD F2 r4 No No Add Yes ADDD F4 F2 F8 Integer No Yes Mult1 Yes MULTD F6 F2 F8 Inteeger No Yes Mult2 No Divide No F0 F2 F4 F6 F8 Integer ADD Mult1 2. 0.9 + 10% of 9 = 1.8 0.9 + 10% of 8 = 1.7 3. b Offset = 1 bits; Index = 2 bits ( use formula given in book ); Tag = 8 -3-1 =4; 2-way associative memory can be depcited as follows: set0 000| |block0 001| |block1 set1 010| |block0 011| |block1 set2 100| |block0 101| |block1 set3 110| |block0 111| |block1 Tag Index Offset r/w set,block h/m prev.tag purge wb 11100 01 1 r 1, 0 m - - - 11100 00 1 w 0, 0 m - y 11100 01 0 w 1, 0 h - - - 10101 10 1 w 2, 0 m - - y 11000 01 0 r 1, 1 m Fill the remaining in the same manner ( Index is used to select a set and Offset to select a block within a set ) I hope this suffices.